A continuing goal of the semiconductor industry has been to increase the memory density (e.g., the number of memory cells per memory die) of memory devices, such as non-volatile memory devices (e.g., NAND Flash memory devices). One way of increasing memory density in non-volatile memory devices is to utilize vertical memory array (also referred to as a “three-dimensional (3D) memory array”) architectures. A conventional vertical memory array includes semiconductor pillars extending through openings in tiers of conductive structures (e.g., word line plates, control gate plates) and dielectric materials at each junction of the semiconductor pillars and the conductive structures. Such a configuration permits a greater number of transistors to be located in a unit of die area by building the array upwards (e.g., longitudinally, vertically) on a die, as compared to structures with conventional planar (e.g., two-dimensional) arrangements of transistors.
Conventional vertical memory arrays include electrical connections between the conductive structures and access lines (e.g., word lines) so that memory cells in the vertical memory array can be uniquely selected for writing, reading, or erasing operations. One method of forming such an electrical connection includes forming a so-called “stair step” (or “staircase”) structure at edges of the tiers of conductive structures. The stair step structure includes individual “steps” defining contact regions of the conductive structures upon which contact structures can be positioned to provide electrical access to the conductive structures.
As vertical memory array technology has advanced, additional memory density has been provided by forming vertical memory arrays to include additional tiers of conductive structures, and, hence, additional steps in the stair step structures associated therewith. However, increasing the number of steps of a stair step structure without undesirably increasing the overall width (e.g., lateral footprint) of the stair step structure can decrease the acceptable margin of error associated with different acts in the process of forming the increased number of steps. A conventional process of forming a stair step structure may include repeated acts of trimming a uniform width of a mask (e.g., photoresist) overlying alternating conductive structures and insulating structures, etching portions of the insulating structures not covered by a remaining portion of the mask, and then etching portions of the conductive structures not covered by remaining portions of the insulating structures. Each of these repeated acts has an associated margin of error permitting the steps of the stair step structure to be suitably sized and positioned to form contact structures thereon. As the number of repeated acts increases, deviation from a desired step width and/or a desired step position may be compounded because errors in the size and/or position of one structure are transferred to subsequently formed structures later in the process. For a large number of steps in the stair step structure, margins of error to achieve suitably sized and positioned steps may be small, such as less than one percent (1%). Achieving such small margins of error can be very difficult using conventional methods, which may result in improperly positioned contact structures and may undesirably decrease yield (e.g., the number of memory cells that are validly programmable and erasable as a percentage of the total number of memory cells in a given batch).
In view of the foregoing, there remains a need for new semiconductor device structures, such as memory array blocks for 3D non-volatile memory devices (e.g., 3D NAND Flash memory devices), as well as for associated semiconductor devices and electronic systems including the new semiconductor device structures, and simple, cost-efficient methods of forming the new semiconductor device structures.